host interface standards support PCI Express a version 1.0. high performance, high reliability and low power consumption Broadocm double integrated MAC + PHY (media access controller and physical interface transceiver) / SERDES chip controller. Each channel, the packet buffer capacity oversized, can reduce CPU usage. Each channel, the double high-speed RISC processors, can perform advanced packet classification. hardware acceleration can divide load host processor task. This controller can be classified load TCP/UDP/IP checksum computation and TCP piecewise task.